We use cookies to enhance your experience on our website. By continuing to use our website, you are agreeing to our use of cookies. You can change your cookie settings at any time. Find out more

A Programmer's View of Computer Architecture

With Assembly Language Examples from the MIPS RISC Architecture

James Goodman and Karen Miller

Publication Date - August 1993

ISBN: 9780195131093

416 pages

Retail Price to Students: $244.99


This introductory text offers a contemporary treatment of computer architecture using assembly and machine language with a focus on software. Students learn how computers work through a clear, generic presentation of a computer architecture, a departure from the traditional focus on a specific architecture. A computer's capabilities are introduced within the context of software, reinforcing the software focus of the text. Designed for computer science majors in an assembly language course, this text uses a top-down approach to the material that enables students to begin programming immediately and to understand the assembly language, the interface between hardware and software. The text includes examples from the MIPS RISC (reduced instruction set computer) architecture, and an accompanying software simulator package simulates a MIPS RISC processor (the software does not require a MIPS processor to run).

Table of Contents

    1. Abstractions and Computers
    1.1. Levels of Abstraction
    1.2. The Tower of Computer Abstractions
    1.3. A Programming Language as an Abstraction
    1.4. Computer Architecture
    1.5. Computer Execution Basics
    2. SAL: A Simple Abstract Language
    2.1. On Assembly and Compilation
    2.2. Variable Declaration
    2.3. Arithmetic Operations
    2.4. Control Structures
    2.5. Communication with the User
    2.6. A SAL Program
    2.7. Procedures
    2.8. A Modular SAL Program
    3. Number Systems
    3.1. Numbers and Their Representation
    3.2. Weighted Positional Notation
    3.3. Transformations Between Radices
    3.4. Representation of Non-Integer Numbers
    3.5. Precision and Accuracy
    4. Data Representation
    4.1. Numbers versus Their Representation
    4.2. Representation of Integers
    4.3. Characters
    4.4. Floating Point Representation
    5. Arithmetic and Logical Operations
    5.1. Boolean Operations
    5.2. Shift Operations
    5.3. Addition and Subtraction
    5.4. Multiplication
    5.5. Division
    6. Floating Point Arithmetic
    6.1. Hardware versus Software Calculations
    6.2. Addition and Subtraction
    6.3. Multiplication
    6.4. Division
    6.5. Advanced Topics
    6.6. SAL Instructions
    7. Data Structures
    7.l. Memory as an Array
    7.2. Arrays
    7.3. Stacks
    7.4. Queues
    8. Registers and MAL
    8.1. Instructions as a Data Type
    8.2. Specifying Addresses in Instructions
    8.3. The MAL Architecture
    8.4. Example MAL Code
    9. Procedures
    9.1. MAL Procedure Call and Return Mechanisms
    9.2. Dynamic Storage Allocation
    9.3. Activation Records
    9.4. Parameter Passing
    9.5. Saving Registers
    9.6. MIPS RISC Register Usage
    9.7. A MAL Program that Uses Procedures
    10. The Assembly Process
    10.1. What Assemblers Do
    10.2. True Assembly Language (TAL)
    10.3. Machine Code Format and Generation
    10.4. Program Relocation
    11. Input and Output
    11.1. Typical I/O Devices
    11.2. The Processor-I/O Interface
    12. Interrupts and Exception Handling
    12.1. The Exception Mechanism
    12.2. The Role of the Operating System
    12.3. The MIPS RISC Exception Mechanism
    12.4. A Sample Exception Handler
    12.5. Operating System Issues
    13. Architectural Performance
    13.1. On Minimal Instruction Sets and Choices
    13.2. Pipelining
    13.3. Branching Techniques
    13.4. Memory Hierarchies
    14. Alternative Architectures
    14.1. What's All This About RISC?
    14.2. The Single-Chip Constraint
    14.3. The Motorola 68000 Family
    14.4. The Intel iAPS 86 Architecture
    14.5. The Cray-1
    14.6. SPARC
    Appendix A. SAL
    Appendix B. MAL
    Appendix C. TAL